It is a fundamental goal in the field of integrated circuit manufacturing to design and manufacture integrated circuits to be as small as possible. As is fundamental in this field, the manufacturing cost of an integrated circuit corresponds strongly to the wafer area occupied by each integrated circuit. Cost can be reduced not only by increasing the number of possible integrated circuits per manufactured wafer, but also by generally providing an increased theoretical yield for a given manufacturing defect density. In addition, the smaller device feature sizes involved in decreasing chip area also provide improved performance, and increased functionality per unit area.
Recent advances in the area of integrated circuit metallization technology have been important in decreasing the necessary chip area for modern integrated circuits. One such advance is the increased number of metal levels that are manufacturable in a device, providing both dramatic reduction in necessary chip area and corresponding dramatic increases in device density. Recent technological advances have also provided significant reductions in the line pitch of conductors in these multiple metal levels, also greatly increasing the functional density of the chip. The advent of copper metallization has also been important in providing reliable small line width conductors in modern integrated circuits.
It is of course important to ensure good electrical isolation between adjacent metal conductors. By way of definition, the insulating material between conductors in the same metallization level is commonly referred to as the intermetal dielectric, or IMD, and the insulating material between conductors in adjacent metallization levels is referred to as the interlayer dielectric, or ILD. For performance and cost reasons, it is desirable to have adjacent conductors as close as possible to one another. This has necessitated the use of so-called “low-k” dielectric materials for the insulator layers between metal conductors. Low-k dielectric materials refers to those insulating materials that have a dielectric constant lower than that of silicon dioxide (that is, having a dielectric constant less than 3.9). Because the capacitance between adjacent conductors depends on the dielectric constant (k) of the insulating material that separates the conductors, as well as the thickness of this insulating material, a low-k dielectric material can be thinner than a higher-k dielectric material, while providing the same or better electrical isolation. The use of low-k dielectric materials is especially important in modern high-frequency integrated circuits.
For 90 nm node devices and beyond, the integration of low-k dielectric materials is required to maintain and improve device performance. Examples of modern low-k dielectric materials include fluorine-doped silicon dioxide (also referred to as fluorinated silicate glass, or FSG), organosilicate glass (OSG), thermoplastic organic polymers, aerogel, xerogel, and other conventional low-k insulator materials. These films, and particularly OSG, have many benefits. However, recently it has been observed that they also have certain drawbacks. Unfortunately, during the manufacturing process, a potential failure mechanism for low-k insulator materials is catastrophic fracture due to fracture resistance (e.g., including but not limited to channel cracking, tunnel cracks, lateral cracks, etc.). The driving force for channel cracking is dependent upon several material properties, with the residual tensile stress, density, hardness, and film modulus of elasticity serving as key factors.
Accordingly, what is needed in the art is a new low-k dielectric material, or a method for manufacturing or treating the traditional low-k dielectric materials, that would reduce or eliminate the aforementioned problems.